In many integrated circuit designs, it is desirable to combine several different transistor technologies, such as ECL (emitter-coupled logic), TTL (transistor- transistor logic), and MOS (metal-on-silicon). In order to combine ECL and TTL technologies, the outputs of the ECL gates must be translated to a logic level suitable for TTL gates. Typically, an ECL gate will use a voltage of -1.6 volts to represent a low logic level (a "0") and will use a voltage of -0.8 volts to represent a high logic level (a "1"). On the other hand, TTL uses a voltage less than 0.4 volts to represent a low logic level and a voltage of greater than 2.7 volts to represent a high logic level. It is important for speed and noise margin considerations that the "trip point" of the TTL, i.e., the voltage at which TTL distinguishes between high and low logic levels, be centered with the transition between high and low ECL logic levels.
In the prior art, ECL-to-TTL level shifters are used between ECL and TTL gates to shift the voltages output from associated ECL circuits. The ECL-to-TTL level shifters add a delay of approximately one nanosecond to the circuit. Since speed is a primary advantage of ECL devices, the slowness of the voltage level shifter is a serious problem. Furthermore, the ECL-to-TTL level shifters increase the power consumed by the integrated circuit.
Therefore, a need has arisen in the industry to provide a method and circuit for converting ECL outputs to TTL logic levels which reduces or eliminates the delay associated with the conversion.